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1/22 september 2004 m68aw512d 8 mbit (512k x16) 3.0v asynchronous sram features summary supply voltage: 2.7 to 3.6v 512k x 16 bits sram with output enable equal cycle and access times: 55, 70ns low standby current low v cc data retention: 1.5v tri-state common i/o automatic power down figure 1. packages bga tfbga48 (zb) 6 x 7mm
m68aw512d 2/22 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . 12 figure 9. chip enable or ub /lb controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . 13 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10.write enable controlled, write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11.chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12.ub /lb controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13.e1 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14.e2 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. low vcc data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15.tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, bottom view package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, package mechanical data . . 19
3/22 m68aw512d part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m68aw512d 4/22 summary description the m68aw512d is an 8 mbit (8,388,608 bit) cmos sram, organized as 524,288 words by 16 bits. the device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. it requires a single 2.7 to 3.6v supply. this device has a chip select pin (e2) for easy memory expansion; when it is active (e2 high) the device has an automatic power-down feature, r educing the power con- sumption by over 99%. the m68aw512d is available in tfbga48 (0.75 mm ball pitch) package. figure 2. logic diagram table 1. signal names ai04800b 19 a0-a18 w dq0-dq15 v cc m68aw512d g 16 e1 ub lb v ss e2 a0-a18 address inputs dq0-dq15 data input/output e1 chip enable e2 chip select g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected du don?t use as internally connected
5/22 m68aw512d figure 3. tfbga connections (top view through package) ai03960 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 du a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 nc ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc v ss v ss dq6 a16
m68aw512d 6/22 figure 4. block diagram ai05452 row decoder a8 a18 (8) dq0 dq15 (8) column decoder i/o circuits a0 a7 w g memory array lb lb ub (8) (8) ub lb e1 e2 ex ub lb
7/22 m68aw512d operation the device has four standard operating modes: output disabled, read, write and standby/pow- er-down. these modes are determined by the control inputs e1 , e1, w , g , lb and ub as sum- marized in table 2.operating modes . output disabled the output enable signal, g , provides high-speed tri-state control of dq0-dq15, allowing fast read/ write cycles on the i/o data bus. the device is in output disabled mode when output enable, g , is high. in this mode, lb and ub are don?t care and dq0-dq15 are high impedance. read mode when chip select (e2) is high, the mvvvvv is in the read mode whenever write enable (w ) is high with output enable (g ) low, and chip en- able (e 1) is asserted. this provides access to data from eight or sixteen, depending on the status of the signal ub and lb , of the 8,388,608 locations in the static memory ar- ray, specified by the 19 address inputs. if only one of the byte enable inputs is at v il , the mvvvvv is in byte read mode. if the two byte enable inputs are at v il , the mvvvvv is in word read mode. so de- pending on the status of the ub and lb signals, valid data will be available on the lower eight, the upper eight or all sixteen output pins, tavqv after the last stable address, providing g is low, e1 is low and e2 is high. if either of e1 or g is asserted after t avqv has elapsed, data access will be measured from the limiting parameter (t elqv , t glqv or t blqv ) rather than the address. data out may be indeterminate at t elqx , t glqx and t blqx , but data lines will al- ways be valid at t avqv . write mode the m68aw512d, when chip select (e2) is high, is in the write mode whenever the w and e1 are low. either the chip enable input (e1 ) or the write enable input (w ) must be de-asserted during ad- dress transitions for subsequent write cycles. when e1 or w is low, and ub or lb is low, write cycle begins on the w or e1 falling edge. when e1 and w are low, and ub = lb = high, write cycle begins on the first falling edge of ub or lb . there- fore, address setup time is referenced to write en- able, chip enables and ub /lb as t avwl , t avel and t avbl respectively, and is determined by the latter occurring falling edge. the write cycle can be terminated by the earlier rising edge of e1 , w , ub and lb . if the output is enabled (e1 = low, e2 = high, g = low, lb or ub = low), then w will return the out- puts to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e1 or for t d- vbh before the rising edge of ub /lb , whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respectively. standby/power-down the m68aw512d has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e1 = high) or chip select is asserted (e2 = low), or ub /lb are de-asserted (ub /lb = high). an output en- able (g ) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w , e1 , lb and ub as summarized in the operating modes ta- ble (see table 2).
m68aw512d 8/22 table 2. operating modes note: 1. x = v ih or v il . operation e1 e2 w g lb ub dq0-dq7 dq8-dq15 power deselected (standby/power-down) v ih xxxxx hi-z hi-z standby (i sb ) x v il xxxx hi-z hi-z standby (i sb ) xxxx v ih v ih hi-z hi-z standby (i sb ) lower byte read v il v ih v ih v il v il v ih data output hi-z active (i cc ) lower byte write v il v ih v il x v il v ih data input hi-z active (i cc ) output disabled v il v ih v ih v ih x x hi-z hi-z active (i cc ) upper byte read v il v ih v ih v il v ih v il hi-z data output active (i cc ) upper byte write v il v ih v il x v ih v il hi-z data input active (i cc ) word read v il v ih v ih v il v il v il data output data output active (i cc ) word write v il v ih v il x v il v il data input data input active (i cc ) output disabled v il v ih x v ih x x hi-z hi-z active (i cc )
9/22 m68aw512d maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for periods greater than 1s may affect device reliability. refer also to the stmicroelec- tronics sure program and other relevant quality documents. table 3. absolute maximum ratings note: 1. up to a maximum operating v cc of 3.6v only. symbol parameter value unit t a ambient operating temperature ?55 to 125 c t stg storage temperature ?65 to 150 c v cc supply voltage ?0.5 to 4.6 v v io (1) input or output voltage ?0.5 to v cc +0.5 v p d power dissipation 1 w
m68aw512d 10/22 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter m68aw512d v cc supply voltage 2.7 to 3.6v ambient operating temperature range 1 0 to 70c range 6 ?40 to 85c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 3.0k ? load resistance (r 2 ) 3.1k ? input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output transition timing reference voltage 0v 0.7v cc 0.3v cc ai05832 v cc out c l includes probe and 1 ttlcapacitance device under test c l r 1 r 2
11/22 m68aw512d table 5. capacitance note: 1. sampled only, not 100% tested. 2. at t a = 25c, f = 1 mhz, v cc = 3.0v. table 6. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e1 = v il and e2 = v ih, lb or/and ub = v il , v in = v il or v ih . 3. e1 0.2v and e2 v cc ?0.2v, lb or/and ub 0.2v, v in 0.2v or v in v cc ?0.2v. 4. output disabled. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 8pf c out output capacitance v out = 0v 10 pf symbol parameter test condition -l -n unit min max min max i cc1 (1,2) operating supply current v cc = 3.6v, f = 1/t avav , i out = 0ma 70ns 25 20 ma 55ns 30 20 ma i cc2 (3) operating supply current v cc = 3.6v, f = 1mhz, i out = 0ma 44ma i sb standby supply current cmos v cc = 3.6v, f = 0, e1 v cc ?0.2v or e2 0.2v or lb =ub v cc ?0.2v 30 30 a i li input leakage current 0v v in v cc ?11?11a i lo output leakage current 0v v out v cc (4) ?11?11a v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.6 ?0.3 0.6 v v oh output high voltage i oh = ?1.0ma 2.4 2.4 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v
m68aw512d 12/22 figure 7. address controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high, ub = low and/or lb = low. figure 8. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high ai05839 tavav tavqv taxqx a0-a18 dq0-dq7 and/or dq8-dq15 valid data valid ai05981b tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a18 e1 g dq0-dq15 valid tblqv tblqx tbhqz ub, lb e2
13/22 m68aw512d figure 9. chip enable or ub /lb controlled, standby mode ac waveforms ai05497 tpd i cc tpu i sb 50% e1, ub, lb e2
m68aw512d 14/22 table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx , t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter m68aw512d unit 55 70 t avav read cycle time min 55 70 ns t av qv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t bhqz (2,3,4) upper/lower byte enable high to output hi-z max 20 25 ns t blqv upper/lower byte enable low to output valid max 55 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 5 ns t ehqz (2,3,4) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3,4) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (1) output enable low to output transition min 5 5 ns t pd chip enable or ub /lb high to power down max 55 70 ns t pu chip enable or ub /lb low to power up min 0 0 ns
15/22 m68aw512d figure 10. write enable controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai05982b tavav twhax tdvwh data input a0-a18 e1 w dq0-dq15 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx tblbh ub, lb e2 telwh
m68aw512d 16/22 figure 11. chip enable controlled, write ac waveforms figure 12. ub /lb controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai05983b tavav tehax tdveh a0-a18 e1 w dq0-dq15 valid taveh tavel tavwl teleh tehdx data input tblbh ub, lb e2 twleh ai05984bc tavav tbhax tdvbh data input a0-a18 e1 w dq0-dq15 valid tavbh tavwl twlqz tbhdx tblbh ub, lb data (1) tavbl e2 twlbh
17/22 m68aw512d table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 3. tested initially and after any design or process changes that may affect these parameters. symbol parameter m68aw512d unit 55 70 t avav write cycle time min 55 70 ns t av bh address valid to lb , ub high min 45 60 ns t avbl addess valid to lb , ub low min 0 0 ns t av eh address valid to chip enable high min 45 60 ns t avel address valid to chip enable low min 0 0 ns t av wh address valid to write enable high min 45 60 ns t avwl address valid to write enable low min 0 0 ns t bhax lb , ub high to address transition min 0 0 ns t bhdx lb , ub high to input transition min 0 0 ns t blbh lb , ub low to lb , ub high min 45 60 ns t bleh lb , ub low to chip enable high min 45 60 ns t blwh lb , ub low to write enable high min 45 60 ns t dvbh input valid to lb , ub high min 25 30 ns t dveh input valid to chip enable high min 25 30 ns t dvwh input valid to write enable high min 25 30 ns t ehax chip enable high to address transition min 0 0 ns t ehdx chip enable high to input transition min 0 0 ns t elbh chip enable low to lb , ub high min 45 60 ns t eleh chip enable low to chip enable high min 45 60 ns t elwh chip enable low to write enable high min 45 60 ns t whax write enable high to address transition min 0 0 ns t whdx write enable high to input transition min 0 0 ns t whqx (1) write enable high to output transition min 5 5 ns t wlbh write enable low to lb , ub high min 45 60 ns t wleh write enable low to chip enable high min 45 60 ns t wlqz (1,2,3) write enable low to output hi-z max 20 20 ns t wlwh write enable low to write enable high min 40 50 ns
m68aw512d 18/22 figure 13. e1 controlled, low v cc data retention ac waveforms figure 14. e2 controlled, low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih v cc ?0.2v or v il 0.2v. 2. tested initially and after any design or process that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min max unit i ccdr (1) supply current (data retention) v cc = 1.5v, e1 v cc ?0.2v or e2 0.2v or ub = lb v cc ?0.2v, f = 0 30 a t cdr (1,2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e1 v cc ?0.2v or e2 0.2v or ub = lb v cc ?0.2v, f = 0 1.5 v ai05985 data retention mode tr 3.6v tcdr v cc 2.7v v dr > 1.5v e1 or ub/lb e1 v dr ? 0.2v or ub = lb v dr ? 0.2v ai05986c data retention mode tr 3.6v tcdr v cc 2.7v v dr > 1.5v e2 e2 < 0.2v
19/22 m68aw512d package mechanical figure 15. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, bottom view package outline note: drawing is not to scale. table 10. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.250 0.400 0.0098 0.0157 a2 0.790 0.0311 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 0.1476 ddd 0.100 0.0039 e 7.000 6.900 7.100 0.2756 0.2717 0.2795 e1 5.250 0.2067 e 0.750 ? ? 0.0295 ? ? fd 1.125 0.0443 fe 0.875 0.0344 sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ? e1 e d1 d e b a2 a1 a bga-z43 ddd fd fe sd se e ball "a1"
m68aw512d 20/22 part numbering table 11. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m68aw512 d l 55 zb 6 t device type m68 mode a = asynchronous operating voltage w = 2.7 to 3.6v array organization 512 = 8 mbit (512k x16) option 1 d = 2 chip enable; write and standby from ub and lb option 2 l = l-die n = n-die speed class 55 = 55ns 70 = 70ns package zb = tfbga48: 0.75mm pitch operative temperature 1 = 0 to 70c 6 = ?40 to 85c shipping t = tape & reel packing
21/22 m68aw512d revision history table 12. document revision history date version revision details july 2001 -01 first issue 06-feb-2002 -02 70ns speed class added, commercial temperature range added 14-mar-2002 -03 document status moved to datasheet tables 2, 7 and 9 clarified figures 8, 9, 10, 11 and 12 clarified 17-jun-2002 -04 block diagram clarified (figure 4) i sb clarified (table 6) i ccdr clarified (table 9) 09-oct-2002 4.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 04 equals 4.0). part number modified. 25-nov-2002 4.2 figure 14, e2 controlled, low vcc data retention ac waveforms , corrected. 01-jul-2003 4.3 tfbga package changed to 6x7mm on page 1 (but not on page 15) values of i cc1 , i sb and i ccdr changed. 16-feb-2004 5.0 datasheet status changed to ?preliminary data?. i cc1 and i sb updated in table 6.dc characteristics . 23-sep-2004 6.0 t pu ad t pd updated in table 7.
m68aw512d 22/22 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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